1. Field of Art
The present invention relates to phase lock loops and, more specifically, to reducing jitter in the output of phase lock loops.
2. Description of the Related Art
Performance requirements for phase lock loops are increasing. For example, video standards are increasing in speed and complexity, resulting in increased performance requirements for phase lock loops used to synchronize the sampling of video signals by clocked analog-to-digital converters as part of video pixel clock reconstruction. In high-definition video systems, differential and integral jitter requirements are particularly stringent due to the higher pixel density of high-definition video standards.
A differential jitter requirement specifies that the adjacent time between edges of a reference signal and edges of an output signal of the phase lock loop shall not depart from those of an ideal clock at the correct center frequency by more than some amount. An integral jitter requirement specifies that, over the period of the reference signal, the placement of the edges of the output signal produced by the phase lock loop shall not depart from those of an ideal clock at the perfect center frequency and perfectly phase locked to the reference signal by some amount. Conventional phase lock loops are unable to produce outputs that meet these increased jitter performance requirements without sacrificing other performance criteria.